1. Technical Field
The present invention relates to a semiconductor device having a digital region and an analog region embedded therein.
2. Background Art
Semiconductor device has a protective structure called seal ring, which is provided around the circumference of the element forming region, having circuits formed therein, for the purpose of protecting the element forming region from influences of external moisture or the like. The seal ring is formed over the entire layers of a multi-layered interconnect structure over a substrate. The seal ring is formed using an electro-conductive film mainly composed of copper, for example, similarly to interconnects and vias formed in the element forming region.
Japanese Laid-Open Patent Publication No. 2008-177246 describes a structure in which guard rings (seal rings) are connected to the ground potential, via contacts and impurity-diffused layers over a substrate. The document describes a technique of appropriately arranging the contacts, in order to suppress operation of parasitic bipolar element otherwise possibly formed by a plurality of guard rings.
Japanese Laid-Open Patent Publication No. 2008-071931 describes a semiconductor device which has a semiconductor chip having an element forming region and a peripheral region formed so as to surround the element forming region, a plurality of metal rings composed of a stack of a plurality of metal layers concentrically formed over the peripheral region of the semiconductor chip, and a stack of a plurality of interconnect layers formed over the element forming region. In a region of an interconnect layer out of the stacked plurality of interconnect layers, neighboring the innermost metal ring (seal ring) out of the plurality of metal rings, a stack of interconnect layers electrically connected in the vertical direction is formed, and the stack of the interconnect layers and the innermost metal ring serve as a pair of electrodes which configure a capacitor having a predetermined potential difference. The stack of the interconnect layers is connected to the source potential, and the innermost metal ring is connected to the ground potential. According to the description, a chip size of a semiconductor device which needs a large capacitor may be reduced.
Published Japanese Translation of PCT International Publication for Patent Application No. 2007-531281 describes that a separated guard ring is connected through a chip metal to a grounding lead wire (paragraph 0033), and that the separated guard ring is connected through the chip metal to a bonding pad which is coupled to the off-chip ground potential (paragraph 0034).
Japanese Laid-Open Patent Publication No. 2004-327941 describes a configuration in which a ring-shape p30-type diffusion region is formed so as to surround an internal circuit on a surface of a P-type substrate and a shunt interconnect is formed in a region containing a right-above region of the p+-type diffusion region on the P-type substrate. The shunt interconnect is connected through a plurality of contacts to the p+-type diffusion region. The shunt interconnect is provided with an annular ring portion which surrounds the internal circuit, and a meander inductor drawn out from the ring portion. One end of the meander inductor is connected to the ground potential interconnect GND, and thereby an oscillation circuit is formed by a contribution of parasitic capacitance ascribable to the P-type substrate and the p+-type diffusion region opposed with the shunt interconnect, and inductance of the shunt interconnect. The description describes that with this structure, a desired frequency component may selectively be removed from substrate noise.
Japanese Laid-Open Patent Publication No. H01-103859 describes that a guard ring (seal ring) is applied with the ground potential.